1. Field of the Invention
The present invention relates to a chopper amplifier circuit apparatus which is formed by, for example, a CMOS circuit, is constituted by utilizing a switched operational amplifier and a chopper modulator, and is operable at a low voltage.
2. Description of the Related Art
Recently, a sensor chip employing a mixed signal CMOS technique has been applied to detection and monitoring of a biological function (See first and second non-patent documents described below, for example). A low noise amplifier is one of the most important circuits in the sensor chip, since the sensor chip detects a low-level signal. However, in the scaled CMOS technique, increase in a direct-current (DC) offset voltage and increase in a low frequency (1/f) noise lead to a serious problem.
Auto-zero operation and chopper stabilization are techniques widely used to reduce these noises (See a third non-patent document described below, for example). Principles of these techniques are shown in FIGS. 15 to 20. FIG. 15 is a circuit diagram showing a configuration of an operational amplifier circuit including an auto-zero operational circuit which is one of principles of noise reduction techniques according to a prior art. FIG. 16 is a timing chart showing control signals φ1 and φ2 for use in the operational amplifier circuit of FIG. 15 for offset cancellation.
Referring to FIG. 15, the operational amplifier circuit including the auto-zero operational circuit is constituted by including a differential operational amplifier 50, an operational amplifier 51, a sample-hold circuit 52 and an adder 53 for forming the auto-zero operational circuit, an adder 54 for adding a DC offset Voff and a 1/f noise Vfn to the output signal from the adder 53, and four switches 55 to 58 operating in response to the control signals φ1 and φ2 for the offset cancellation.
Referring to FIG. 16, the control signal φ2 has a high level only during an offset cancellation interval, and the control signal φ1 becomes the high level from a low level after the end of the offset cancellation interval. According to the auto-zero operation technique, noises such as the DC offset Voff and the 1/f noise Vfn at zero input are sampled, and thereafter, a noise effect caused by a feedback is subtracted from an input signal by the auto-zero operational circuit constituted by the operational amplifier 51, the sample-hold circuit 52, and the adder 53. The auto-zero operation technique thus makes it possible to reduce the low-frequency noises of the amplifier circuit, however, one problem of the auto-zero operation technique is to increase in a baseband noise floor caused by aliasing of a broadband noise unique to a sampling process.
FIG. 17 is a circuit diagram showing a configuration of a chopper amplifier circuit of an operational amplifier including a chopper stabilizing circuit, which is one of the principles of noise reduction techniques according to the prior art. FIG. 18 is a timing chart showing control signals φ1 and φ2 for use in the operational amplifier circuit of FIG. 17 for chopper modulation and chopper demodulation. Referring to FIG. 18, the control signals φ1 and φ2 have a predetermined chopper frequency fc and are complementally to each other. In this case, a chopper cycle Tc is a reciprocal of the chopper frequency fc. In addition, FIG. 19 is a diagram showing a frequency characteristic of an input voltage signal Vin(f) inputted to the chopper amplifier circuit of FIG. 17, FIG. 20 is a diagram showing a frequency characteristic of an input voltage signal V(f) inputted to an operational amplifier 60 of the chopper amplifier circuit of FIG. 17, and FIG. 21 is a diagram showing a frequency characteristic of an output voltage signal Vout(f) outputted from a chopper demodulator 62 of the chopper amplifier circuit of FIG. 17, and a frequency characteristic of an output voltage signal outputted from a low-pass filter 63.
Referring to FIG. 17, the chopper amplifier circuit is constituted by including a differential operational amplifier 60, a chopper modulator 61 which is provided at the previous stage of the operational amplifier 60 and constituted by four switches 71 to 74, an adder 64 which is provided at the previous stage of the operational amplifier 60 for adding the DC offset Voff and the 1/f noise Vfn to the output signal from the chopper modulator 61, the chopper demodulator 62 which is provided at the subsequent stage of the operational amplifier 60 and constituted by four switches 81 to 84, and the low-pass filter 63 which is provided at the subsequent stage of the chopper demodulator 62 and inserted at a final stage of the chopper amplifier circuit for extracting a desired input signal. According to the chopper stabilization based on a modulation technique, a chopper-modulated signal is obtained by converting a frequency range of an input signal having a frequency spectrum of FIG. 19 into a higher frequency range by the chopper modulator 61 (See FIG. 20). The DC offset Voff and the 1/f noise Vfn are added to the chopper-modulated signal at the previous stage of the operational amplifier 60. A resultant chopper-modulated signal is amplified by the operational amplifier 60, is chopper-demodulated by the chopper demodulator 62, and is processed by the low-pass filter 63 so as to obtain an input signal that is an original baseband signal (See FIG. 21). It is noted that a level of the 1/f noise Vfn is smaller than that of a thermal noise. In the chopper amplifier circuit, a large energy due to by the low-frequency noise is generated by the chopper demodulation using the chopping frequency fc, however, a cleaner output signal can be obtained by using the low-pass filter 63 employed in the chopper stabilization technique.
A combination of the auto-zero operation technique and the chopper stabilization technique can contribute to reduce the baseband noise floor and modulation noise at the chopper frequency, since the auto-zero operation eliminates the DC offset and the chopper stabilization reduces the baseband noise (See a fourth non-patent document described below, for example).
The following prior art documents are related to the present invention:
(1) first non-patent document: K. D. Wise, “Wireless implantable Microsystems: Coming breakthroughs in health care”, Symposium on VLSI Circuits Digest of Technical Papers, pp. 106-109, June 2002;
(2) second non-patent document: T. Yoshida et al., “A design of neural signal sensing LSI with multi-input-channels”, IEICE Transactions Fundamentals, Vol. E87-A, No. 2, pp. 376-383, February 2004;
(3) third non-patent document: C. C. ENZ et al., “Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization”, Proceedings of the IEEE, Vol. 84, No. 11, pp. 1584-1614, November 1996;
(4) fourth non-patent document: A. T. K. Tang, “A 3 μV-Offset Operational Amplifier with 20 nV/√{square root over (Hz)} Input Noise PSD at DC Employing both Chopping and Autozeroing”, ISSCC Digest of Technical Papers, pp. 386-387, February 2002;
(5) fifth non-patent document: A. M. Abo et al., “A 1.5-V, 10-bit 14.3-MS/s CMOS pipeline analog-to-digital converter”, Journal of Solid State Circuits, Vol. 34, No. 5, pp. 599-606, May 1999;
(6) sixth non-patent document: V. Cheung et al., “A 1V CMOS Switched-Opamp Switched-Capacitor Pseudo-2-Path Filter”, ISSCC Digest of Technical Papers, pp. 154-155, February 2000;
(7) seventh non-patent document: Q. Huang, C. Menolfi, “A 200 nV offset 6.5 nV/√{square root over (Hz)} Noise PSD 5.6 kHz Chopper Instrumentation Amplifier in 1 μm Digital CMOS”, ISSCC Digest of Technical Papers, pp. 362-363, February 2001; and
(8) eighth non-patent document: J. F. Duque-Carrillo et al., “1-V Rali-to Rali Operational Amplifiers in Standard CMOS Technology”, Journal of Solid State Circuits, Vol. 35, No. 1, pp. 33-44, January 2000.
The above-mentioned two techniques are required for a low noise amplifier operating at a low voltage, however, it is difficult to apply the two techniques to the low noise amplifier by utilizing an ordinary analog switch. The reason for the difficulty is that the analog switch cannot transmit an intermediate voltage level by using a low power source voltage. In order to solve this problem of the analog switch, a clock signal boosting technique (See the fifth non-patent document, for example) and a switched operational amplifier technique (See the sixth non-patent document, for example) have been developed. The above-mentioned reason will be described below in detail with reference to FIGS. 22 and 23.
FIG. 22 is a circuit diagram showing a configuration of a CMOS analog switch circuit according to a prior art. FIG. 23 is a graph showing operation of the CMOS analog switch circuit of FIG. 22 and conductances Gp and Gn of respective MOSFETs P101 and N101 with respect to an input voltage Vin. The conductance Gp of the P channel MOSFET P101 and the conductance Gn of the N channel MOSFET N101 which constitute the CMOS analog switch of FIG. 22, decrease at the input voltage near Vdd/2 even in an ON-state when a power source voltage Vdd is reduced to, for example, one volt, and this leads to that the analog switch can not turned on. Under these conditions, there was such a problem that it was difficult to realize an electronic circuit utilizing the analog switch such as an A/D converter, a D/A converter or a DC amplifier circuit.
Namely, in recent fine CMOS processing, the power source voltage Vdd is gradually made lower according to a device scaling law, however, a threshold voltage Vth of a CMOS device is not made lower in order to reduce the power consumption during standby of a large-scaled digital circuit. For example, in a CMOS process with the power source voltage Vdd of 1.0 V and the threshold voltage Vth of 0.5 V, a floating analog switch is put into an off-state when the input signal has an intermediate electric potential, and then, a chopper circuit for switching over among signal paths cannot be realized (See FIGS. 22 and 23). In order to realize the analog switch operating even at a low power source voltage, there have been a boot-strapping technique for boosting a gate voltage of a transistor and a low threshold voltage device for use in analog circuits. However, in the former case, such a device is required that has a withstand voltage higher than that of an ordinary device, and this causes problems complication of process, deterioration in reliability, and an increase in circuit area. In addition, in the latter case, there are problems of an increase in a leakage current and deterioration in reliability.